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The security cell of the CSR decode PAL on the CMD CQD-200/TM is programmed which prevents simply reading the array pattern out of the CSR decode PAL with a device programmer to program a duplicate CSR decode PAL.
I had to resort to reverse engineering the CMD CQD-200/TM CSR decode PAL to program a new CSR decode PALs for the MTI QTS-30 controllers to convert them to CQD-200/TM controllers.
The inputs to the CSR decode PAL were not too difficult to trace to their sources. The inputs are the CSR and Bootstrap Address Select jumpers W4-1 through W4-5 and the Q-Bus signals BDAL2 through BDAL12, BBS7, and BSYNC. The Q-Bus signals had to be traced from the card edge fingers through the AM2908 and DS8641 Bus Transceivers to the CSR decode PAL.
The outputs were not too difficult to determine how they must be setup. One pin of the CSR decode PAL was traced to the W7 Auto-Boot Enable jumper and was determined to be the bootstrap ROM select. In addition to the bootstrap ROM select there must also be either a disk CSR select and a tape CSR select, or a single CSR select plus a disk/tape CSR indicator. The setup used is a single CSR select plus a disk/tape CSR indicator. This was determined by removing the CSR decode PAL from the CQD-200/TM and feeding the inputs with a digital pattern generator and observing the outputs with a logic analyzer.
One last CSR decode PAL pin was traced to the clock input of the 74F175 flip-flop U44. This output was determined to be simply the BSYNC signal passed though the PAL, most likely to synchronize the flop-flop clock input with the propagation delay of the CSR decode outputs of the PAL which were also traced to data inputs of the same flip-flop.
The traced Q-Bus signals from the from the card edge fingers through the AM2908 and DS8641 Bus Transceivers to the CSR decode PAL and the CSR and Bootstrap Address Select jumpers W4 are listed below:
U53 AM2908 Quad Bus Tranceivers-------------------------------BV2 BDAL15 PIN 4 BUS0 PIN 2 R0BU2 BDAL14 PIN 6 BUS1 PIN 8 R1BT2 BDAL13 PIN 14 BUS2 PIN 12 R2BS2 BDAL12 PIN 16 BUS3 PIN 18 R3 -> PAL PIN 13U54 AM2908 Quad Bus Tranceivers-------------------------------BR2 BDAL11 PIN 4 BUS0 PIN 2 R0 -> PAL PIN 11BP2 BDAL10 PIN 6 BUS1 PIN 8 R1 -> PAL PIN 10BN2 BDAL9 PIN 14 BUS2 PIN 12 R2 -> PAL PIN 9BM2 BDAL8 PIN 16 BUS3 PIN 18 R3 -> PAL PIN 8U55 AM2908 Quad Bus Tranceivers-------------------------------BL2 BDAL7 PIN 4 BUS0 PIN 2 R0 -> PAL PIN 7BK2 BDAL6 PIN 6 BUS1 PIN 8 R1 -> PAL PIN 6BJ2 BDAL5 PIN 14 BUS2 PIN 12 R2 -> PAL PIN 5BH2 BDAL4 PIN 16 BUS3 PIN 18 R3 -> PAL PIN 4U56 AM2908 Quad Bus Tranceivers-------------------------------BF2 BDAL3 PIN 4 BUS0 PIN 2 R0 -> PAL PIN 3BE2 BDAL2 PIN 6 BUS1 PIN 8 R1 -> PAL PIN 2AV2 BDAL1 PIN 14 BUS2 PIN 12 R2AU2 BDAL0 PIN 16 BUS3 PIN 18 R3U57 AM2908 Quad Bus Tranceivers-------------------------------BF1 BDAL21 PIN 4 BUS0 PIN 2 R0BE1 BDAL20 PIN 6 BUS1 PIN 8 R1BD1 BDAL19 PIN 14 BUS2 PIN 12 R2BC1 BDAL18 PIN 16 BUS3 PIN 18 R3U58 AM2908 Quad Bus Tranceivers-------------------------------AM2 BIAKI PIN 4 BUS0 PIN 2 R0BA1 BDCOK PIN 6 BUS1 PIN 8 R1AD1 BDAL17 PIN 14 BUS2 PIN 12 R2AC1 BDAL16 PIN 16 BUS3 PIN 18 R3U63 DS8641 Quad Unified Bus Transceiver---------------------------------------AR1 BREF PIN 1 BUS3 PIN 3 OUT 3AR2 BDMGI PIN 4 BUS4 PIN 6 OUT 4AF2 BRPLY PIN 12 BUS2 PIN 10 OUT 2AJ2 BSYNC PIN 15 BUS1 PIN 13 OUT 1 -> PAL PIN 14U64 DS8641 Quad Unified Bus Transceiver---------------------------------------AP2 BBS7 PIN 1 BUS3 PIN 3 OUT 3 -> PAL PIN 1AT2 BINIT PIN 4 BUS4 PIN 6 OUT 4AE2 BDOUT PIN 12 BUS2 PIN 10 OUT 2AH2 BDIN PIN 15 BUS1 PIN 13 OUT 1U44 74F175 Quad D-Type Flip-Flop--------------------------------PAL PIN 17 -> PIN 13 D3PAL PIN 18 -> PIN 9 CLKPAL PIN 20 -> PIN 4 D0W4 Jumpers CSR and Bootstrap Address Select-------------------------------------------W4-1 -> PAL PIN 15W4-2 -> PAL PIN 23W4-3 -> PAL PIN 22W4-4 -> PAL PIN 21W4-5 -> PAL PIN 16W7 Jumpers Auto-Boot Enable---------------------------PAL PIN 19 -> w7-1
The resulting annotated pinout of the CSR decode PAL is shown in the figure below:
+---------\ /---------+ | \ / | | ----- | BBS7 | 1 24 | Vcc | | BDAL2 | 2 23 | W4_2 | | BDAL3 | 3 22 | W4_3 | | BDAL4 | 4 21 | W4_4 | | BDAL5 | 5 20 | CsrSelect | | BDAL6 | 6 19 | RomSelect | | BDAL7 | 7 18 | FFClock | | BDAL8 | 8 17 | CsrIsTape | | BDAL9 | 9 16 | W4_5 | | BDAL10 | 10 15 | W4_1 | | BDAL11 | 11 14 | BSYNC | | GND | 12 13 | BDAL12 | | | | `---------------------------'The CSR and Bootstrap Address Select jumpers W4-1 through W4-5 are documented with the following settings in the CMD CQD-200/TM manual: Bootstrap Address W4-1Disk CSR Address W4-2 W4-3Tape CSR Addrress W4-4 W4-5Given the inputs to the CSR decode PAL and the documented settings of the CSR and Bootstrap Address Select jumpers W4-1 through W4-5 the following CSR decode PAL equations were derived:
Address = [1, 1, 1, 1, 1, 1, 1, 1, 1, BDAL12, BDAL11, BDAL10, BDAL9, BDAL8, BDAL7, BDAL6, BDAL5, BDAL4, BDAL3, BDAL2, 0, 0]; DiskSel = [W4_2, W4_3]; TapeSel = [W4_4, W4_5]; DiskSelect = BBS7 & (((Address == ^o17772150) & (DiskSel == 0)) # ((Address == ^o17760334) & (DiskSel == 1)) # ((Address == ^o17760354) & (DiskSel == 2))); TapeSelect = BBS7 & (((Address == ^o17774500) & (TapeSel == 0)) # ((Address == ^o17760404) & (TapeSel == 1)) # ((Address == ^o17760444) & (TapeSel == 2))); CsrSelect = DiskSelect # TapeSelect; CsrIsTape = TapeSelect; RomSelect = BBS7 & (Address >= ^o17773000) & (Address <= ^o17773777) & !W4_1; RomSelect = BBS7 & (Address >= ^o17771000) & (Address <= ^o17771777) & W4_1; FFClock = BSYNC;The complete derived Abel source code for the CSR decode PAL is attached below along with the compiled report file. |
CMD CQD-200 SCSI >
