It says "arrow computers D5-SE100P"
Card |
Card |
||||||||||||||||||||||||||||||||||||||||||||||||||
M8192
|
GRC-RXV2 DG-Corp 27-0028-0E |
||||||||||||||||||||||||||||||||||||||||||||||||||
NS memory card (no ID
yet)
Manual Jumpers DELQA DELQA+ |
|||||||||||||||||||||||||||||||||||||||||||||||||||
M8061- RL01/02 disk
controller RLV12As delivered: M10 M9 M8 M7 M6 M5 M4 M3 is +5 V8 V7 V6 V5 V4 V3 V2 0 1 1 1 1 1 0 3 7 0 370 M22 M21 M20 M19 M18 M17 M16 M15 M14 M13 M12 M11 GND A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 +5 1 1 1 0 1 1 1 0 0 X 7 7 3 4 0 7777340 22bit M1<->2 Parity error abort M24<->M25 |
|||||||||||||||||||||||||||||||||||||||||||||||||||
Emulex UU0110401 (1983)
or THIS?(1984)
rev B UC0110201-L1G Seagate S1210N drive IBM WDS 380 IBM WDS 380 RQDX3 22bit SW2.7 774400 sw6.1 controller vector 0 160 SW2.1 controller vector 1 214 SW2.2 RLV12 configured NOT RLV11 LTC enabled SW4.9 - WHY? Bootstrap 765000 or 773000 0713 B W/BOOTSTRAP |
|||||||||||||||||||||||||||||||||||||||||||||||||||
Sigma Information DZV11 Ass 400310 manual |
GTSC 304B 304 manual |
||||||||||||||||||||||||||||||||||||||||||||||||||
ASYN LINE INTR (320)
8017(see page404) DLV11-E berg pinouts M8017 |
SIGMA INTERNATIONAL 400310 DZV11 400310 manual |
Factory defaults |
Mine |
||
Jumper |
Stats |
Function |
|
W1 |
Installed |
Bit 15 set |
Installed |
2 |
Installed |
Bit 14 set |
Installed |
3 |
Removed |
Selects power-up option 2 |
Removed |
4 |
Installed |
Bit 13 set |
Installed |
5 |
Removed |
Halt traps to 4 |
Installed |
6 |
installed |
bit 12 set |
Installed |
7 |
Installed |
Selects power-up option 2 |
Installed |
8 |
Removed |
Wakeup enabled |
Removed |
9 |
Removed |
BEVNT reg enabled |
Removed |
There are 4 leds visible on the back of the CPU board: d4 mem, d3 slu, d2 cpu, d1 odt \ / M8192 \ / -----------------------^^^^----------- | |||| | | D4 D1 | | | | | | | | E36 Microprocessor | | | | o-o W9 | | o-o | o-o o-o o-o W5 o-o o-o o-o o-o W1 | | | | | | | E34 E13 | | Cache State | | Control Sequencer | | | |_ _ _| |_______________| |________________| B A
INSTALLATION:
2.1 INTRODUCTION
This chapter discusses the considerations and requirements to
configure and install a KDJ11-A module in an LSI-11 system. The
module can be installed in systems using the extended LSI-11 bus
backplane as well as existing systems that use one of the standard
LSI-11 backplanes. The items that must be considered before
installing the module are as follows.
1. Configuration of the user selectable features.
2. Selection of an LSI-l I compatible backplane and mounting box.
3. Selection of LSI-l 1 options compatible with the KDJ11-A.
4. Knowledge of system differences when replacing an LSI-11
processor
with the KDJ11-A module.
2.2 CONFIGURATION
The KDJ11-A has nine jumpers for the user selectable features. The
locations of these jumpers are shown in Figure 2- 1 and their
functions are described in Table 2-1 . A jumper is installed by
pushing an insulated jumper wire (P/N 1 2-1 8783-00) onto the two
wirewrap pins provided on the module.
Table 2-1 KDJ11-A Jumper Identification Jumper Function w1 Bootstrap address bit 15 W2 Bootstrap address bit 14 W3 Power-up option selection bit 02 W4 Bootstrap address bit 13 w5 HALT trap option bit 03 W6 Bootstrap address bit 12 W7 Power-up option selection bit 01 W8 Wakeup disable W9 BEVNT recognition
2.2.1 Power-Up Options
There are four power-up options available for the user to select.
These options are selected by jumpers W7 and W3. The bits are set
(1) when the jumpers are removed. A power-up option is selected by
configuring W3 and W7, as described in Table 2-2. A description of
each option is provided below.
Power-Up Options Option W3 W7 Power-Up Mode 0 Installed Installed PC at 24, PS = 26 1 Installed Removed Micro-ODT, PS = 0 2 Removed Installed PC at 173000, P5 = 340 3 Removed Removed Users bootstrap, PS at 340Option 0: The processor reads physical memory locations 24 and 26 and loads the data into the PC and PS, respectively. The processor either services pending interrupts or starts program execution, beginning at the memory location pointed at by the PC.
Option 1: The processor unconditionally enters micro-ODT with the PS cleared. Pending service conditions are ignored.
Option 2: The processor sets the PC to 173000 and the PS to 340. The processor then either services pending interrupts or starts program execution, beginning at the memory location pointed at by the PC. This option is used for the standard bootstrap.
Option 3: The processor reads the four bootstrap address jumpers
and loads the result into PC
2.2.2 HALT Option
The HALT option determines the action taken after a HALT
instruction is executed in the kernel mode. At the end of a HALT
instruction, the processor checks the BPOK bit 00 before checking
the HALT option bit 03. If BPOK is set, the processor will
recognize the HALT option, which is controlled by the W5 jumper.
When the jumper is removed, bit 03 is set (1) and the processor
will trap to location 4 in the kernel data space and set bit 07 of
the CPU error register. When the jumper is installed, bit 03 reads
as a zero and the processor enters the micro-ODT mode. If BPOK bit
00 is not set when the processor checks, the option is not
recognized and the processor loops until BPOK is asserted and the
power-up sequence is initiated.
2.2.3 Boot Address
The boot address jumpers selects the starting address for the
user’s bootstrap program when power-up option 3 is selected. The
state of the highest four bits, <15:12>, is determined by
jumpers W1, W2, W4, and W6, respectively. A bit will be set (1)
when the respective jumper for that bit is installed and the bit
will be read as a zero when the jumper is removed. During the
power-up sequence, the processor reads the address determined by
bits <15:12> and forces the remaining bits to read as zeros.
Therefore, the user’s bootstrap program can reside on any 2048
word boundary.
2.2.4 Wakeup Disable
The KDJ11-AA module has an onboard wakeup circuit to properly
sequence the BDCOK signal. When jumper W8 is removed, the wakeup
circuit is enabled and the module will properly sequence the BDCOK
signal. The wakeup circuit will be disabled when W8 is installed
and external logic must be used to properly sequence the BDCOK
signal.
2.2.5 BEVNT Recognition
The LSI-11 bus signal BEVNT provides an external event interrupt
request to the processor. This feature is disabled when the W9
jumper is installed and disables the line time clock register.
When the jumper is removed, the BEVNT input is recognized and is
under control of the line time clock register. Specifically, the
signal is recognized by the module when bit 06 of the line time
clock register is set (1) and is disabled when bit 06 is not set
(0). The line time clock register address is 17 777 546 and is a
read/write register.
2.2.6 Factory Configuration
The factory or shipped configuration is described in Table 2-3.
The user should review these features and change them accordingly
to match the requirements of the system using the module.
Factory Configuration Jumper Status Function W1 Installed Bit 15 set (I) W2 Installed Bit 14 set (1) W3 Removed Selects power-up option 2 W4 Installed Bit 13 set (1) W5 Removed HALT instruction traps to location 4 W6 Installed Bit 12 set (1) W7 Installed Selects power-up option 2 W8 Removed Wakeup circuit is enabled W9 Removed BEVNT register is enabledDIAGNOSTIC LEDS
LED Functions LED On Test Conditions Dl Micro-ODT is entered. D2 Module could not do a write and read transaction to the CPU error register. Indicates the microcode is not running. D3 Module attempted to read location 17 777 560 and timed out. Indicates SLU is not responding. D4 Module attempted to read location 0 and timed out or attempted to read location 17 777 700 and did not timeout. Indicates the memory system is not responding. Probable System Failure LEDs Dl D2 D3 D4 Probable Failure X On On On CPU module X Off On On LSI-11 bus X On Off On CPU module X Off Off On LSI-11 bus or memory X On On Off CPU module X Off On Off SLU module X On Off Off CPU module X Off Off Off Console terminal